Because of this, all but the most trivial SoCs require communications subsystems.
Originally, as with other microcomputer technologies, data bus architectures were used, but recently designs based on sparse intercommunication networks known as networks-on-chip NoC have risen to prominence and are forecast to overtake bus architectures for SoC design in the near future. Historically, a shared global computer bus typically connected the different components, also called "blocks" of the System-on-Chip.
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Direct memory access controllers route data directly between external interfaces and SoC memory, bypassing the CPU or control unit , thereby increasing the data throughput of the system-on-chip. This is similar to some device drivers of peripherals on component-based multi-chip module PC architectures.
Computer buses are limited in scalability , supporting only up to tens of cores multicore on a single chip. These challenges are prohibitive to supporting manycore systems on chip.
In the late s , a trend of systems-on-chip implementing communications subsystems in terms of a network-like topology instead of bus-based protocols has emerged. A trend towards more processor cores on SoCs has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost.
Networks-on-chip have advantages including destination- and application-specific routing , greater power efficiency and reduced possibility of bus contention. Network-on-chip architectures take inspiration from networking protocols like TCP and the Internet protocol suite for on-chip communication,  although they typically have fewer network layers.
Optimal network-on-chip network architectures are an ongoing area of much research interest. NoC architectures range from traditional distributed computing network topologies such as torus , hypercube , meshes and tree networks to genetic algorithm scheduling to randomized algorithms such as random walks with branching and randomized time to live TTL.
Many SoC researchers consider NoC architectures to be the future of system-on-chip design because they have been shown to efficiently meet power and throughput needs of SoC designs. Current NoC architectures are two-dimensional.
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The design flow for an SoC aims to develop this hardware and software at the same time, also known as architectural co-design. Most SoCs are developed from pre-qualified hardware component IP core specifications for the hardware elements and execution units , collectively "blocks", described above, together with software device drivers that may control their operation. Of particular importance are the protocol stacks that drive industry-standard interfaces like USB.
The hardware blocks are put together using computer-aided design tools, specifically electronic design automation tools; the software modules are integrated using a software integrated development environment. Once the architecture of the SoC has been defined, any new hardware elements are written in an abstract hardware description language termed register transfer level RTL which defines the circuit behavior, or synthesized into RTL from a high level language through high-level synthesis.
These elements are connected together in a hardware description language to create the full SoC design.
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The logic specified to connect these components and convert between possibly different interfaces provided by different vendors is called glue logic. Chips are verified for logical correctness before being sent to a semiconductor foundry.